1. Field of the Invention
The present invention relates to a method of manufacturing a non-volatile memory device and, more particularly, to a method of manufacturing a silicon-oxide-nitride-oxide-semiconductor (SONOS) flash memory device.
2. Background of the Related Art
With the development of high-capacity memory devices, non-volatile memory devices are being increasingly important. An example of the non-volatile memory device is a flash memory device. A conventional flash memory device is a single type in which a gate structure is formed in a single cell. As shown in FIG. 1, the conventional flash memory device can indicate two states, i.e., state “1” and state “0”.
However, the single type flash memory device cannot satisfy requirements for high-integration although it is a good device in itself. Thus, a multi bit cell, which has at least two gate structures in a single cell, has been developed. In addition, to embody the multi bit cell, a silicon-oxide-nitride-oxide-semiconductor (SONOS) structure has been proposed.
A flash memory device employing the SONOS structure is a kind of transistor and comprises an oxide-nitride-oxide (ONO) layer, as a non-volatile insulating material, formed on a substrate, a silicon gate formed on the ONO layer, and a source/drain region formed at both sides of the gate. As shown in FIG. 2, the SONOS flash memory device can control turn-on current capacity of a transistor, based on where electrons are injected, and, as shown in FIG. 3, indicate four states, i.e., state “11”, state “10”, state “01”, and state “00”. Therefore, the SONOS flash memory device can satisfy more or less the most recent requirement for high-integration.
A conventional SONOS flash memory device is described in detail. FIG. 4 illustrates, in a top view, a cell array of a conventional SONOS flash memory device. FIG. 5 is a cross-sectional view of FIG. 4 taken along the line A-A′ and FIG. 6 is a cross-sectional view of FIG. 4 taken along the line B-B′. In FIGS. 4 through 6, “40” is a semiconductor substrate, “42” is a device isolation layer, “43” and “45” are oxide layers, “44” is a nitride layer, and “46” is a gate. As shown in FIGS. 4 through 6, a cell has a symmetrical structure and a source region and a drain region are respectively placed at both sides of the gate.
The SONOS flash memory device, like general non-volatile memory devices, provides three operations, that is, read, program, and erase. In program operation, if an appropriate program voltage is applied to the flash memory device, hot electrons are generated and captured by tunneling in a tunnel nitride layer adjacent to a drain. Therefore, a threshold voltage of a transistor increases and data programming is performed. In erase operation, if an appropriate erase voltage is applied to the flash memory device while a gate, a source, and a drain are open, the hot electrons captured in the tunnel nitride layer are forced out from the substrate. Therefore, a threshold voltage of the transistor is lowered and data erasing is performed. In read operation, if an appropriate read voltage is applied to the flash memory device, data reading is performed when a sensing circuit senses an electric current flowing between the source and the drain.
However, in the conventional SONOS flash memory device, the nitride layer cannot completely prevent the electrons from traveling therein although the nitride layer is an insulator, thereby causing cell malfunction because electrons captured in one side of the tunnel nitride layer travel to another side. Accordingly, the conventional SONOS flash memory device cannot ensure device characteristics and reliability because of the electron movement in the tunnel nitride layer.